As microprocessors that achieve high-speed processing, pipeline operators that use pipeline processing have been used. The pipeline processing employs a method of overlapping the processing of a plurality of instructions by delaying the starting time of the execution of each instruction one clock by one clock, thereby achieving the execution of the instructions at an equivalent high speed. Before installing a pipeline operator into a computer system, the installation area, power consumption, and price of the pipeline operator are important factors that need to be examined. The pipeline operator must meet compactness, low power consumption, and low price as essential conditions.
FIG. 27 is a diagram that shows a structure of a conventional pipeline operator. The pipeline operator shown in this drawing has two processing stages of a first processing stage and a second processing stage. An operator 221 and an operator 122 to be described later are provided at the first processing stage and the second processing stage respectively. A processing-data register 10 is provided corresponding to a pipeline path P10, and holds a first processing data (source operand). A processing-data register 20 is provided corresponding to a pipeline path P20, and holds a second processing data (source operand). An instruction register 30 is provided corresponding to an instruction pipeline path P30, and holds an instruction INST1 and an instruction INST2. The instruction INST1 is a processing instruction dispatched to the operator 221, and the instruction INST2 is a processing instruction dispatched to the operator 122.
Further, according to the conventional pipeline operator, a plurality of stage latch circuits for temporarily holding data and instructions are provided at an input stage of the two processing stages, between the first processing stage and the second processing stage (inter-processing stage), and at an output stage of the two processing stages, respectively. Specifically, a stage latch circuit 111, a stage latch circuit 211 and a stage latch circuit 311 are provided in parallel at the input stage. A stage latch circuit 112, a stage latch circuit 212 and a stage latch circuit 312 are provided in parallel between the processing stages, and a stage latch circuit 113 is provided at the output stage. The stage latch circuit 111 and the stage latch circuit 112 are sequentially driven in one clock cycle in such a order of the input stage→the processing stage→the output stage.
At the first processing stage, the stage latch circuit 111 is provided corresponding to the processing-data register 10, and holds the first processing data from the processing-data register 10. The stage latch circuit 211 is provided corresponding to the processing-data register 20, and holds the second processing data from the processing-data register 20. The stage latch circuit 311 is provided corresponding to the instruction register 30, and holds the instruction INST1 and the instruction INST2 from the instruction register 30. The instruction decoder 32, decodes the instruction INST1 from the stage latch circuit 311. When the instruction INST1 has been decoded, the operator 221 executes the processing according to the instruction INST1 by using the value (the first processing data) of the stage latch circuit 111 and the value (the second processing data) of the stage latch circuit 211. Then, the operator 221 outputs the result of the processing to the stage latch circuit 212 through the pipeline path P20.
At the second processing stage, the stage latch circuit 112 is provided corresponding to the processing-data register 10, and holds the value of the stage latch circuit 11, (the first processing data). The stage latch circuit 212 is provided corresponding to the processing-data register 20, and holds the result of the processing by the operator 221. The stage latch circuit 312 is provided corresponding to the instruction register 30, and holds the values of the stage latch circuit 311 (instruction INST1 and the instruction INST2). The instruction decoder 322 decodes the instruction INST2 from the stage latch circuit 312. When the instruction INST2 has been decoded, the operator 122 executes the processing according to the instruction INST2 by using the value (the first processing data) of the stage latch circuit 112, and outputs the result of the processing through the pipeline path P10.
A multiplexer 402 is a two-input and one-output type changeover unit whose changeover is controlled by the instruction decoder 322. The multiplexer 402 outputs one of the processing result of the operator 122 and the value of the stage latch circuit 212 (the processing result of the operator 221). Specifically, the multiplexer 402 outputs the processing result of the operator 122 when the instruction INST2 has been decoded by the instruction decoder 322. On the other hand, the multiplexer 402 outputs the value of the stage latch circuit 212 when the instruction other than the instruction INST2 (for example, the instruction INST1) has been input to the instruction decoder 322. The stage latch circuit 113 holds the processing result of the operator 122 or the value of the stage latch circuit 212 (the processing result of the operator 221) according to the changeover state of the multiplexer 402. A processing-result register 50 holds a value of the stage latch circuit 113, that is, a processing result (a destination operand) of the pipeline operator.
The operation of the conventional pipeline operator will be explained here. The operation when the instruction INST1 has been dispatched will be explained first. At the first clock, the first processing data, the second processing data and the instruction INST1 are held in the processing-data register 10, the processing-data register 20 and the instruction register 30 respectively. At the next clock, the first processing data, the second processing data and the instruction INST1 are held in the stage latch circuit 111, the stage latch circuit 211 and the stage latch circuit 311 respectively. Then, the instruction decoder 321 decodes the instruction INST1 from the stage latch circuit 311. The operator 221 executes the processing according to the instruction INST1 by using the value (the first processing data) of the stage latch circuit 111 and the value (the second processing data) of the stage latch circuit 211.
At the next clock, the value (the first processing data) of the stage latch circuit 111, the processing result of the operator 221 and the value (the instruction INST1) of the stage latch circuit 311 are held in the stage latch circuit 112, the stage latch circuit 212 and the stage latch circuit 312 respectively. In this case, as the value (instruction INST1) of the stage latch circuit 312 is irrelevant to the instruction according to the operator 122, the instruction decoder 322 makes the multiplexer 402 select the stage latch circuit 212.
At the next clock, the value (the processing result of the operator 221) of the stage latch circuit 212 is held in the stage latch circuit 113 through the multiplexer 402. As a result, the processing-result register 50 holds the processing result of the operator 221 as the processing result of the pipeline operator.
The operation when the instruction INST2 has been dispatched will be explained next. At the first clock, the first processing data, the second processing data and the instruction INST2 are held in the processing-data register 10, the processing-data register 20 and the instruction register 30 respectively in the similar manner to that of the above operation. At the next clock, the first processing data, the second processing data and the instruction INST2 are held in the stage latch circuit 111, the stage latch circuit 211 and the stage latch circuit 311 respectively. In this case, as the value (instruction INST2) of the stage latch circuit 311 is irrelevant to the instruction according to the operator 221, the instruction decoder 321 does not decode the instruction. Therefore, the operator 221 executes no processing in this case.
At the next clock, the value (the first processing data) of the stage latch circuit 111 and the value (the instruction INST2) of the stage latch circuit 311 are held in the stage latch circuit 112 and the stage latch circuit 312 respectively. In this case, the instruction decoder 322 decodes the instruction INST2 from the stage latch circuit 312, and at the same time, makes the multiplexer 402 select the operator 122. As a result, the operator 122 executes the processing according to the instruction INST2 by using the value (the first processing data) of the stage latch circuit 112.
At the next clock, the processing result of the operator 122 is held in the stage latch circuit 113 through the multiplexer 402. As a result, the processing-result register 50 holds the processing result of the operator 122 as the processing result of the pipeline operator.
As explained above, as shown in FIG. 27, the conventional pipeline operator is provided with the stage latch circuit 112 for holding the first processing data (source operand) from the processing-data register 10. Furthermore, the pipeline operator is provided with the stage latch circuit 212 for holding the processing result of the operator 221, independent of the stage latch circuit 112. In this structure, the first processing data held in the processing-data register 10 is input to the operator 122 through the stage latch circuit 111 and the stage latch circuit 112. On the other hand, the processing result of the operator 221 is input to the multiplexer 402 through the stage latch circuit 212.
According to the conventional pipeline operator, because the stage latch circuit 11, and the stage latch circuit 212 are provided independent of each other between the first processing stage and the second processing stage, as explained above, the circuits (the stage latch circuits, the wiring and the control circuits) have redundant structures. Accordingly, the conventional pipeline operator poses a problem because it requires a large scale of hardware, and as a result has high power consumption.